// 一秒计时器实现
module timer_1 (
    input clk,
    input rst_n,
    output wire end_cnt_1s

);

    parameter TIME_1S = 3000_000;
    reg [25:0] cnt;
    wire add_cnt;
    wire end_cnt;

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) cnt <=0;
        else if(add_cnt)
            if(end_cnt) cnt <=0;
            else cnt <= cnt + 1'b1;
        else cnt <= cnt;
    end

    assign add_cnt = 1'b1;
    assign end_cnt = add_cnt && (cnt == TIME_1S );
    
    assign end_cnt_1s = end_cnt;

endmodule